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APPROVED PRODUCT
SC680E
SMBus System Clock Buffer
Product Features
18 output buffer for high clock fanout applications Each output can be internally disabled for EMI reduction VDD=3.3 volts for chip Vdd Output frequency range 10 Mhz to 100 Mhz < 250ps skew between output clocks 48-pin SSOP package Single Clock Enable pin for testability
Product Description
The SC680 is a high fanout system clock buffer. Its primary application is to create the large quantity of clocks needed to support a wide range of applications that requires those clock loads signal that are referenced to a single existing clock. Loads of up to 30 pF are supported. One of the chief applications of this component is where long traces are used to transport clocks from their generating devices to their loads. The creation of EMI and the degradation of waveform rise and fall times is greatly reduced by running a single reference clock trace to this device and then using it to regenerate the clock that drives shorter traces. Using these devices EMI is therefore minimized and board real estate is saved.
Block Diagram
VDD CLK[1:2] VDD CLK[3:4] REFIN VDD CLK[5:6] VDD CLK[7:8] VDD CLK[9:10] VDD CLK[11:12] OE SDATA SCLK VDD
Pin Configuration
IMISC680
NC NC VDD CLK1 CLK2 VSS VDD CLK3 CLK4 VSS REFIN VDD
CLK[15:16] VDD CLK[17,18]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
NC NC VDD CLK18 CLK17 VSS VDD CLK15 VSS OE VDD CLK14 CLK13 VSS VDD CLK12 CLK11 VSS VDD CLK10 VSS VSS SCLOCK CLK16
Control Logic
CLK[13:14] VDD
CLK5 CLK6 VSS VDD CLK7 CLK8 VSS VDD CLK9 VSS VDD SDATA
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Cypress Semiconductor Corporation 3901 North First St. San Jose, CA 95134. Tel: 408-943-2600 http://www.cypress.com
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Document#: 38-07026 Rev. *A
12/17/2002 Page 1 of 10
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APPROVED PRODUCT
SC680E
SMBus System Clock Buffer
Pin Description
PIN No. 11 4,5 8,9 13, 14 17, 18 21, 28 31, 32 35, 36 40, 41 44, 45 38 Pin Name REFIN CLK(1:2) CLK(3:4) CLK(5:6) CLK(7:8) CLK(9:10) CLK(11:12) CLK(13:14) CLK(15:16) CLK(17:18) OE PWR VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD I/O I O O O O O O O O O I TYPE PAD BUF1 BUF1 BUF1 BUF1 BUF1 BUF1 BUF1 BUF1 BUF1 PAD Description This pin is connected to the input reference clock. This clock must be in the range of 10.0 to 100.0 Mhz. Low skew output clock Low skew output clock Low skew output clock Low skew output clock Low skew output clock Low skew output clock Low skew output clock Low skew output clock Low skew output clock Buffer Output Enable pin. When driven to a logic low level this pin is used to place all output clocks (CLK1:18} in a tri state condition. This feature facilitates in production board level testing to be easily implemented for the clocks that this device produces. Has internal pull-up resistor. serial data of SMBus 2-wire control interface. Has internal pullup resistor. Serial clock of SMBus 2-wire control interface. Has internal pullup resistor. Ground pins for clock output buffers. These pins must be returned to the same potential to reduce output clock skew.
24 25 6, 10, 15, 19, 22, 30, 34, 39, 43 3, 7, 12, 16, 20, 33, 37, 42, 46 29, 23 26, 27
SDATA SDCLK Vss
-
I/O I PWR
PAD PAD -
Vdd
-
PWR
-
Power for output clock buffers.
Vdd Vss
-
PWR PWR
-
Power for core logic. Ground supply pins for internal lcore logic pins.
Cypress Semiconductor Corporation 3901 North First St. San Jose, CA 95134. Tel: 408-943-2600 http://www.cypress.com
Document#: 38-07026 Rev. *A
12/17/2002 Page 2 of 10
APPROVED PRODUCT
SC680E
SMBus System Clock Buffer
2-Wire SMBus Control Interface The 2-wire control interface implements a write only slave interface. The device cannot be read back. Sub-addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock output to be individually enabled or disabled. During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledgement is generated. The first byte of a transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first. The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on the SDATA wire following reception of each byte. The device will not respond to any other control interface conditions. Previously set control registers are retained. Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated. Following the acknowledge of the Address Byte (D2), two additional bytes must be sent: 1) "Command Code " byte, and 2) "Byte Count" byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1, Byte 2, ....) will be valid and acknowledged.
Cypress Semiconductor Corporation 3901 North First St. San Jose, CA 95134. Tel: 408-943-2600 http://www.cypress.com
Document#: 38-07026 Rev. *A
12/17/2002 Page 3 of 10
APPROVED PRODUCT
SC680E
SMBus System Clock Buffer
Serial Control Registers (Cont.) Byte 0: Function Select Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 1 0
@Pup 1 1 1 1 1 1 1 1
Pin# 18 17 14 13 9 8 5 4
Description CLK8 (Active = 1, Forced low = 0) CLK7 (Active = 1, Forced low = 0) CLK6 (Active = 1, Forced low = 0) CLK5 (Active = 1, Forced low = 0) CLK4 (Active = 1, Forced low = 0) CLK3 (Active = 1, Forced low = 0) CLK2 (Active = 1, Forced low = 0) CLK1 (Active = 1, Forced low = 0)
Byte 1: Clock Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 45 44 41 40 36 35 32 31 Description CLK18 (Active = 1, Forced low = 0) CLK17 (Active = 1, Forced low = 0) CLK16 (Active = 1, Forced low = 0) CLK15 (Active = 1, Forced low = 0) CLK14 (Active = 1, Forced low = 0) CLK13 (Active = 1, Forced low = 0) CLK12 (Active = 1, Forced low = 0) CLK11 (Active = 1, Forced low = 0)
Byte 2: Clock Register (1 = enable, 0 = Stopped)
Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 0 0 0 1 1 Pin# 28 21 Description CLK10 (Active = 1, Forced low = 0) CLK9 (Active = 1, Forced low = 0) Not Used Not Used Not Used Not Used Not Used Not Used
Cypress Semiconductor Corporation 3901 North First St. San Jose, CA 95134. Tel: 408-943-2600 http://www.cypress.com
Document#: 38-07026 Rev. *A
12/17/2002 Page 4 of 10
APPROVED PRODUCT
SC680E
SMBus System Clock Buffer
Maximum Ratings
1
This device contains circuitry to protect the inputs against damage due to high static voltages or electric Voltage Relative to VSS: Voltage Relative to VDD: Storage Temperature: Operating Temperature: Maximum Power Supply: -0.3V 0.3V -65C to + 150C 0C to +70C 7V field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)Electrical Characteristics
Characteristic Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 40mA Output High Voltage IOH = 30mA Tri-State leakage Current Dynamic Supply Current Idd100 Static Supply Current Short Circuit Current Input Rise Time Isdd ISC VIR 12 25 2.4 220 4 mA mA mA nS Symbol VIL VIH IIL IIH VOL VOH Ioz Idd66 2.4 9 Min 2.0 -66 66 0.4 10 160 Typ Max 0.8 Units Vdc Vdc A A Vdc Vdc A mA Input frequency = 66 Mhz - All outputs on and at 30 pF load Input frequency 100 Mhz - All outputs on and at 30 pF load All outputs disabled no input clock 1 output at a time - 30 seconds .8 to 2.4 volts All Outputs (see buffer spec) All Outputs Using 3.3V Power (see buffer spec) Conditions -
VDD = VDD1 thru VDD9 =3.3V 5%, , TA = 0C to +70C
1
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Cypress Semiconductor Corporation 3901 North First St. San Jose, CA 95134. Tel: 408-943-2600 http://www.cypress.com
Document#: 38-07026 Rev. *A
12/17/2002 Page 5 of 10
APPROVED PRODUCT
SC680E
SMBus System Clock Buffer
Switching Characteristics
Characteristic Output Duty Cycle Buffer out/out Skew All Buffer Outputs Buffer input to output Skew Jitter Cycle to Cycle* Jitter Absolute (Peak to Peak)* Symbol tSKEW tSKEW TJCC TJabs Min 45 2.0 Typ 50 0 Max 55 250 5.0 100 150 Units % pS nS pS pS @ 30 pF loading @ 30 pF loading Conditions Measured at 1.5V (50/50 in) 35 pF Load Measured at 1.5V
VDD = VDD1 thru VDD9 = 3.3V 5%, , TA = 0C to +70C *This jitter is additive to the input clock's jitter.
TB40_ Type Buffer Characteristics (All Clock Outputs)
Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Dynamic Output Impedance Rise/Fall Time Min Between 0.4 V and 2.4 V Rise/Fall Time Max Between 0.4 V and 2.4 V Symbol IOHmin IOHmax IOLmin IOLmax ZO TRFmin TRFmax Min 30 75 30 75 8 0.5 0.5 Typ Max 39 109 40 103 15 1.33 1.33 Units mA mA mA mA Ohms nS nS Conditions Vout = VDD - .5V Vout = 1.5 V Vout = 0.4 V Vout = 1.2 V 66-100 MHz 30 pF Load 30 pF Load
VDD = VDD1 thru VDD9 =3.3V 5%, , TA = 0C to +70C
Cypress Semiconductor Corporation 3901 North First St. San Jose, CA 95134. Tel: 408-943-2600 http://www.cypress.com
Document#: 38-07026 Rev. *A
12/17/2002 Page 6 of 10
APPROVED PRODUCT
SC680E
SMBus System Clock Buffer
PCB layout Suggestion
Via to VDD Plane Via to GND Plane Void (cut) in power plane
C1
C2
C3
C4
C5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
C11
FB2 VCC
C10 C9 C12 22uF
C8
C7
C6
This is only a layout recommendation for best performance and lower EMI. the designer may choose a different approach but C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, and C11 (all are 0.1 uf) should always be used and placed as close to their VDD pins as is physically possible.
Cypress Semiconductor Corporation 3901 North First St. San Jose, CA 95134. Tel: 408-943-2600 http://www.cypress.com
Document#: 38-07026 Rev. *A
12/17/2002 Page 7 of 10
APPROVED PRODUCT
SC680E
SMBus System Clock Buffer
Packing Drawing and Dimensions 48 Pin SSOP Outline Dimensions
INCHES C L E H SYMBOL A A1 A2 B c D A2 A1 B e A D
a
MILLIMETERS MAX 0.110 0.016 0.095 0.0135 0.010 0.637 0.299 MIN 2.41 0.20 2.16 0.203 0.127 15.75 7.39 NOM 2.59 0.31 2.29 0.254 0.20 15.88 7.49 0.640 BSC 0.420 0.040 8 10.03 0.61 0 10.36 0.76 4 10.67 1.02 8 MAX 2.79 0.41 2.41 0.343 0.254 16.18 7.59
MIN 0.095 0.008 0.085 0.008 0.005 0.620 0.291
NOM 0.102 0.012 0.090 0.010 .008 0.625 0.295 0.0256 BSC
E e H L a
0.395 0.024 0
0.408 0.030 4
Ordering Information
Part Number SC680EYB Package Type 48 PIN SSOP Production Flow Commercial, 0C to +70C
Note:
The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Cypress SC680EYB Date Code, Lot #
Marking: Example:
SC680EYB Flow B = Commercial, 0C to + 70C Package Y = SSOP Revision Device Number
Cypress Semiconductor Corporation 3901 North First St. San Jose, CA 95134. Tel: 408-943-2600 http://www.cypress.com
Document#: 38-07026 Rev. *A
12/17/2002 Page 8 of 10
APPROVED PRODUCT
SC680E
SMBus System Clock Buffer
Notice Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of its products in the life supporting and medical applications.
Cypress Semiconductor Corporation 3901 North First St. San Jose, CA 95134. Tel: 408-943-2600 http://www.cypress.com
Document#: 38-07026 Rev. *A
12/17/2002 Page 9 of 10
APPROVED PRODUCT
SC680E
SMBus System Clock Buffer
Document Title: SC680E SMBus System Clock Buffer Document Number: 38-07026
Rev. ** *A
ECN No. 106954 122724
Issue Date 06/29/01 12/17/02
Orig. of Change IKA RBI
Description of Change Convert from IMI to Cypress Added power-up requirements to maximum ratings information.
Cypress Semiconductor Corporation 3901 North First St. San Jose, CA 95134. Tel: 408-943-2600 http://www.cypress.com
Document#: 38-07026 Rev. *A
12/17/2002 Page 10 of 10

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